Hi! I'm Alec

A QUBO-based optimization framework for silicon vacancy configurations, achieving 7× speedup over exhaustive search via simulated annealing while maintaining ground-state accuracy (R² > 0.95 vs. DFT). Extended to boron-doped silicon and validated on real quantum hardware using QuEra Aquila via AWS Braket.

Optimized L3 cache integration for IBM z18 (Samsung 3nm) by advancing custom RTL-to-GDSII flow stages.

An intuitive DevOps dashboard that automates and visualizes PD CI metrics, replacing 80+ pages of manual spreadsheets with clear, configurable summaries and Slack integration.

Taped out a 1×1 mm 65nm TSMC mixed-signal image sensor in TSMC 65nm, featuring a modular 5×3 pixel array, custom bias network, and scan chains—demonstrating full DRC/LVS compliance and post-layout simulation functionality for IoT vision systems.

Designed and built a 40% scale, laser-cut replica of the Avatar Tsko A'eoio bow for a VR archery game, featuring layered wood limbs, etched leather grip, and modular acrylic feathers for durability and repairability.

An in-depth exploration and optimization of clock tree topologies in IBM microprocessors, leveraging new FO2/FO4 configurations and Spider2 routing to reduce power and improve timing metrics under strict design constraints.

Developed a fully functional 6T SRAM in 28nm TSMC with DRC/LVS clean layout, verified timing closure, and integrated scan-based read/write verification across multiple instances.

I built a supervised convolutional neural network (CNN) to automatically detect and segment magnetic bubble domains from high-resolution Lorentz TEM images. Starting from raw image data, I labeled domain regions, processed the dataset, and trained the network to distinguish bubbles from background noise with high accuracy—enabling fast, automated analysis that would otherwise require labor-intensive manual inspection.

Taped out a 1×1 mm 28nm ASIC integrating a ResNet accelerator and RISC-V CPU for real-time radio signal classification—delivering over 73× speedup compared to the FPGA baseline—with an extended 2×1.25 mm version integrating a Strip Spectral Correlation Analyzer for full spectral analysis.

Engineered a novel aluminum gate stack alternative to polysilicon, pushing the boundaries of cleanroom process integration. Through strategic oxide growth, contamination control, and electrical testing, this demo uncovered critical scaling limits—and paved the way for next-gen PECVD and sputtered gate dielectrics.