Hi! I'm Alec

What started as a deep dive into the physics of silicon—defects, interfaces, and material behavior quickly turned into an obsession with shaping that silicon into something functional. I have gone from studying transistors to floorplanning, timing, and taping them out in full-chip designs.

About Me

About Me Portrait
  • I'm Alec, a 23-year-old physical design engineer from Chicago with a passion for building high-performance hardware systems
  • Currently a CPU Physical Design & Integration Intern at IBM and pursuing an M.S. in ECE at Carnegie Mellon University, where I earned dual B.S. degrees in ECE and MSE
  • I'm passionate about physical implementation—where form meets function at the nanoscale. I aim to design efficient, next-gen ASICs that push the limits of performance, power, and scalability
  • I want to contribute to architectures that define the future of computing
  • In my free time, I'm a major American football enthusiast and part-time rowing coach

Experience

IBM

CPU Physical Design and Integration Intern

May 2025 – Present

  • Optimized floorplan, placement, and timing for the z18 L3 cache using IBM’s internal physical design flow
  • Closed the majority of critical timing violations across L3 partitions, reducing worst slack by 86%
  • Coordinated top and block level integration, aligning interface constraints across hierarchical partitions
Skills: Cadence, Tcl
IBM

CPU Clock Physical Design and DevOps Intern

May 2024 – Aug 2024

  • Curated and analyzed 12 new clock tree topologies in Cadence Virtuoso for application in IBM microprocessors
  • Reduced P11 microprocessor clock power by 4% through FO2 buffer prioritization and identifying fan out power trends
  • Automated continuous integration metric aggregation to streamline Release Delivery Automation reports
Skills: Cadence, Tcl, CTS, Python, Pandas, JSON, MongoDB
Argonne National Laboratory

Nanoscale Heterostructures Researcher

Jun 2022 – Jun 2024

  • Generated and trained a CNN image classification pipeline for automated identification of skyrmions in LTEM images
  • Attained 95% segmentation accuracy and published results in AIP Advances (2024)
Skills: C, Python, Go, CNN, PyTorch, CUDA, NumPy, Pandas, TEM
Northwestern University

Physical Electronics Research Laboratory (PERLab) Researcher

May 2023 – October 2023

  • Created a neural network utilizing spin waves and skyrmions for computational functions
  • Constructed a PCB implementing voltage-controlled magnetic anisotropy (VCMA) for random number generation
Skills: Python, SystemVerilog, C, Go, CNN, Altium, CUDA, PyTorch, NumPy
Sonovia Ltd.

Laboratory Assistant

June 2021 – August 2021

  • Conduct laboratory experiments involving sample preparation and data collection. Established protocols include either titration or sonication
  • Maintain lab by ordering new lab supplies and sterilizing equipment
  • Perform product research in antibacterial and water-resistant markets
Skills: Wet Lab, Titration, Sonication, Lab Management

Projects

Skills

Cadence

Cadence

Synopsys

Synopsys

SystemVerilog

SystemVerilog

Python

Python

C

C

Tcl

Tcl

Assembly

Assembly x86/ARM/RISC-V

Linux

Linux

Jenkins

Jenkins

JFrog

JFrog

TSMC PDK

TSMC PDK

Samsung PDK

Samsung PDK